1. Field of the Invention
The present invention relates to a method, of manufacturing a display unit of a flat display panel having a wide viewing angle, to reduce the required masks in the fabrication process.
2. Description of the Related Art
Liquid crystal display panels (hereinafter referred to as LCD panels) are among the most popular-flat display panels. Recently, LCD panels of the fringe field switch (FFS) type have been developed. Generally a display unit (or pixel unit) in a LCD panel of the FFS type has pixel electrodes and common electrodes, which are made of transparent indium-tin oxide layers (hereinafter referred to as ITO layers) thereby increasing the brightness of the LCD panel. The pixel electrodes of the display unit in the FFS-type LCD panel are formed in a comb shape or a multi-finger shape and the common electrodes of the FFS-type LCD panel are formed in a plate shape. In addition, pixel electrodes of comb shape or multi-finger shape generally are provided over the common electrodes.
The electrode structure of a display unit in an FFS-type LCD panel is prevalent in fabricating a LCD panel having a wide viewing angle. The LCD panel having a wide viewing angle, for instance the IPS (in-plane switch) LCD panel or FOP (finger-on-panel) LCD panel, has a similar electrode structure to that of the FFS-type LCD panel.
The electrode structure of the FOP LCD panel requires two fabricating processes for ITO layers, therefore increasing the number of masks and the manufacturing cost.
FIGS. 1A to 1G show, in a cross-sectional view, the process of fabricating a pixel unit of a FOP LCD panel having a wide viewing angle in a conventional art.
First, a first metal layer (M1) is formed on a substrate 100, for example, a glass substrate. Secondly, a first photolithography process (using the first mask) is carried out to pattern and then etch the first metal layer (M1) to form a gate layer 101 and a bottom electrode layer 102 on the substrate 100, as depicted in FIG. 1A.
A first isolation layer 103 is formed over the substrate 100. Then, an active layer is formed on the first isolation layer 103. The active layer, for example, is an amorphous silicon layer or a polysilicon layer.
A second photolithography process (using the second mask) is carried out to pattern and then etch the active layer to form an island-like layer 104 overlaying the gate layer 101, as depicted in FIG. 1B.
Then, a second metal layer (M2) is formed over the substrate 100.
A third-photolithography process (using the third mask) is carried out to pattern and then etch the second metal layer (M2) to form a first source/drain electrode 105, a second source/drain electrode 106, a top electrode layer 107, and a common contact layer 108, as depicted in FIG. 1C.
It is noted that the first and second source/drain electrodes (105, 106) respectively overlap side portions of the island-like layer 104 and the island-like layer 104 is revealed between the first and second source/drain electrodes (105, 106). The bottom electrode layer 102, the top electrode layer 107, and the first isolation layer 103 constitute a storage capacitor of the pixel unit in the FOP LCD panel.
A second isolation layer (referred to as a planarization layer) 109 is then formed over the substrate 100.
A fourth photolithography process (using the fourth mask) is further carried out to pattern and then etch the second isolation layer 109 to reveal the first source/drain electrode 105 and the top electrode layer 107, as depicted in FIG. 1D.
Next, a first ITO layer is formed on the second isolation layer 109.
A fifth photolithography process (using the fifth mask) is carried out to pattern and then etch the first ITO layer so as to form a common electrode layer 110, as depicted in FIG. 1E. The common electrode layer 110 is electrically connected to both the first source/drain electrode 105 and the top electrode layer 107.
Next, a planarized isolation layer 111 and a TEOS layer 112 are sequentially formed over the substrate 100. Then, a sixth photolithography process (using the sixth mask) is carried out to pattern and then etch the TEOS layer 112 and the planarized isolation layer 111 so as to reveal the common contact layer 108, as depicted in FIG. 1F.
A second ITO layer is formed on the TEOS layer 112. A seventh photolithography process (using the seventh mask) is carried out to pattern and then etch the second ITO layer so as to form pixel electrodes, as depicted in FIG. 1G. The pixel electrodes form in a multi-finger shape or a comb shape.
It is obvious from the above descriptions that seven masks are required to fabricate a display unit of a FOP LCD panel. Seven masks are more than that required to fabricate the FFS-type TFT LCD panel and more costly.
Therefore, an object of the present invention is to provide a method of manufacturing a display unit of a flat display panel having a wide viewing angle while reducing the number of masks and the cost of fabrication.
The present invention achieves the above-indicated objects by providing a method comprising the following steps.
(a) Form a first conduction layer on a substrate.
(b) Pattern and etch the first conduction layer to form a gate layer and a bottom electrode layer on the substrate.
(c) Form a first isolation layer on the substrate.
(d) Form an active layer on the first isolation.
(e) Pattern and etch the active layer to form an island-like layer over the gate layer.
(f) Form a second conduction layer over the substrate.
(g) Pattern and etch the second conduction layer to form a first and second source/drain electrodes, a top electrode layer, and a common contact layer. It is noted that the first and second source/drain electrodes respectively overlap side portions of the island-like layer revealing the island-like layer therebetween, and the bottom electrode layer, the first isolation layer, and the top electrode layer constitute a storage capacitor of the displaying unit of the flat display panel.
(h) Form a second isolation layer over the substrate.
(i) Form a third conduction layer on the second isolation layer.
(j) Pattern and etch the third and second isolation layers to form a first contact hole, a second contact hole, a third contact hole, a fourth contact hole, and at least a fifth contact hole. It is noted that the first source/drain electrode is revealed in the first contact hole, the common electrode layer is revealed in the second and third contact holes, the top electrode layer is revealed in the fourth contact hole, and the common contact layer is revealed in the fifth contact hole.
(k) Form a third isolation layer over the substrate.
(l) Pattern and etch the third and second isolation layers to form a first contact hole, a second contact hole, a third contact hole, a fourth contact hole, and at least a fifth contact hole. It is noted that the first source/drain electrode is revealed in the first contact hole, the common electrode layer is revealed in the second and third contact holes, the top electrode layer is revealed in the fourth contact hole, and the common contact layer is revealed in the fifth contact hole.
(m) Form a fourth conduction layer on the third isolation layer and respectively fill in the first to fifth contact holes.
(n) Pattern and etch the fourth conduction layer to form a plurality of pixel electrodes, a first connecting layer, and a second connecting layer on the third isolation layer. It is noted that the first source/drain electrode in the, first contact hole and the common electrode layer in the second contact hole are electrically connected via the first connecting layer, the common electrode layer in the third contact hole and the top electrode layer in the fourth contact hole are electrically connected via the second connecting layer, and the pixel electrodes electrically connect to the common contact layer through the fifth contact hole.